  module converter(
input clk,
input rst,
output wire[7:0] data,
output wire[7:0] data1,
output reg clk_div   
);

parameter inc = 2; //1,2,...10
parameter taken = 4;//
parameter amp =2;//

wire clk_25M;
wire locked;
wire rst_lo;

 reg clk_64k;
reg[7:0] cnt;
reg[11:0] count;
reg[3:0] div;

assign data1 = (cnt < 64/taken)? 256/amp : 0 ;

pll_clk u_pll_clk(
.areset (~rst),
.inclk0 (clk),
.c0	(clk_25M),
.locked (locked)
);

assign rst_lo = rst && locked ;


always @(posedge clk_25M or negedge rst_lo) begin
if(rst_lo == 1'b0) begin
count <= 1'b0;
clk_64k <= 1'b0; 
end else if(count < 98) count <= count + 1'b1;
else begin 
clk_64k <= ~clk_64k; 
count <= 1'b0;
end
end

always @(posedge clk_64k or negedge rst_lo) begin
if(rst_lo == 1'b0) begin
div <= 1'b0;
clk_div <= 1'b0; 
end else if(div < inc) div <= div + 1'b1;
else begin 
clk_div <= ~clk_div; 
div <= 1'b0;
end
end

always @(posedge clk_div or negedge rst_lo) begin
if(rst_lo == 1'b0) cnt <= 1'b0;
else if(cnt < 63 ) cnt <= cnt + 8'b00000001;
else if(cnt == 63) cnt <= 0;
else cnt <= cnt; 
end

rom_ip u_rom_ip(
.address (cnt),
.clock (~clk_div),
.q (data)
);

endmodule